Structured ZnO-based contacts deposited by non-reactive rf magnetron sputtering on ultra-thin SiO2/Si through a stencil mask

In this paper, we study the localized deposition of ZnO micro and nanostructures deposited by non-reactive rf-magnetron sputtering through a stencil mask on ultra-thin (10 nm) SiO2 layers containing a single plane of silicon nanocrystals (NCs), synthetized by ultra-low energy ion implantation followed by thermal annealing. The localized ZnO-deposited areas are reproducing the exact stencil mask patterns. A resistivity of around 5×10−3 Ω cm is measured on ZnO layer. The as-deposited ZnO material is 97% transparent above the wavelength at 400 nm. ZnO nanostructures can thus be used as transparent electrodes for Si NCs embedded in the gate-oxide of MOS devices

Ambipolar silicon nanowire FETs with stenciled-deposited metal gate

We report on a fully CMOS compatible fabrication method for ambipolar silicon nanowire FinFETs. The low thermal budget processing, compatible with monolithic 3D device integration, makes use of low pressure chemical vapor deposition (LPCVD) of amorphous Si (a-Si) and SiO2 layers as well as metal gate patterning using stencil lithography, demonstrated for the first time. FinFETs with stenciled Al gates are successfully co-fabricated with polycrystalline silicon Ω-gated devices. Stencil lithography is envisaged as a key enabler for gate patterning on 3D structures, such as vertically stacked nanowire transistors

Ambipolar silicon nanowire FETs with stenciled sub-µm metal gate

A fully CMOS compatible fabrication flow using low temperature a-Si LPCVD and stencil lithography has been developed and proved suitable for SiNW FinFETs having ambipolar conductance. The stencil mask has been demonstrated to be a real option for sub-micrometer metal gate patterning for the first time. It is worth noting that the flexibility of this process enables the deposition of several gate materials, bypassing the conventional fabrication issues related to material etch selectivity. Finally, the excellent performance of individual FinFETs paves the way for the fabrication of more complex circuits

Stenciled conducting bismuth nanowires

Stencil lithography is used here for the fabrication of bismuth nanowires using thermal evaporation. This technique provides good electrical contact resistance by having the nanowire structure and the contact pads deposited at the same time. It has also the advantage of modulating nanowires' height as a function of their width. As the evaporated material deposits on the stencil mask, the apertures shrink in size until they are fully clogged and no more material can pass through. Thus, the authors obtain variable-height (from 27 to 95 nm) nanowires in the same evaporation. Upon their morphological (scanning electron microscopy and atomic force microscopy) and electrical characterizations, the authors obtain their resistivity, which is independent of the nanowire size and is the lowest reported for physical vapor deposition of Bi nanowires (1.2×10−3 Omega cm), only an order of magnitude higher than that of bulk bismuth

Organic Thin Film Transistors on Flexible Polyimide Substrates Fabricated by Full Wafer Stencil Lithography

This paper presents new results on miniaturized organic thin film transistors (TFT) fabricated on a spin coated polyimide (PI) film. Patterning steps, that are vital for the integrity and electrical performances of the organic TFT, were performed using resistless shadow-mask lithography with two high precision MEMS fabricated stencils, thus avoiding solvents and high temperature processes. Both pentacene and source-drain (S/D) electrodes were directly patterned through stencils with high accuracy on wafer scale. The TFT have been characterized before and after peeling the flexible PI film off the rigid surface, showing full transistor functionality in both cases

Analysis of the blurring in stencil lithography

A quantitative analysis of the blurring and its dependence on the stencil-substrate gap and the deposition parameters in stencil lithography, a high resolution shadow mask technique, is presented. The blurring is manifested in two ways: first, the structure directly deposited on the substrate is larger than the stencil aperture due to geometrical factors, and second, a halo of material is formed surrounding the deposited structure presumably due to surface diffusion. The blurring is studied as a function of the gap using dedicated stencils that allow a controlled variation of the gap. Our results show a linear relationship between the gap and the blurring of the directly deposited structure. In our configuration, with a material source of ~5 mm and a source-substrate distance of 1 m, we extract that ~10 micrometers of gap enlarge the directly deposited structures by ~50 nm. The measured halo varies from 0.2 to 3 micrometers in width depending on the gap, the stencil aperture size and other deposition parameters. We also show that the blurring can be reduced by decreasing the nominal deposition thickness, the deposition rate and the substrate temperature

Three-level stencil alignment fabrication of a high-k gate stack organic thin film transistor

In this work a high-k double-gate pentacene field-effect transistor architecture is presented. The devices are fabricated on a flexible polyimide substrate by three aligned levels of stencil lithography combined with standard photolithography. ALD-deposited high-k HfO2 and parylene D device passivation, together with Pt top-gate deposition provide very good electrostatic control of the channel, showing low leakage current and improved subthreshold. The ION/IOFF ratio is of the order of 106 and the IOFF lower than 0.1 pA/μm. We also report a comparison of the normal, FET-like (VD 0) modes of the p-OFET. We find a higher current drive in the reverse diode-like mode compared to normal FET-like mode. The reverse mode has clearly defined OFF and ON states versus the drain voltage and non-saturated output characteristics, which makes it suitable for the use in RF and analog applications of OFETs

Reusability of nanostencils for the patterning of Aluminum nanostructures by selective wet etching

One of the major advantages of stencil lithography is the possibility to use stencils many times. However, when stencils contain nanoapertures, the clogging of the membranes limits the useful life time of the stencils. The clogging is due to the accumulation of material deposited inside the apertures of the stencil. Here, we report a study on the effect of the clogging on the life time of stencils after Al depositions through the stencils. Then we present a method to clean the stencils based on Al wet etching to eliminate the clogging. We show that this method allows the reusability of stencils for the repeatable depositions of Al nanostructures